India's semiconductor strategy: the state of play

The bet

India consumes a large and rising volume of semiconductors and, until recently, made almost none of them. The India Semiconductor Mission, launched in 2021 under the Ministry of Electronics and IT, is a state-backed attempt to change that through large capital incentives for fabrication, assembly-test-packaging and design. Its policy parent is the National Policy on Electronics 2019, which named facilitating wafer-fabrication facilities as an explicit state objective. The wager is that India can convert its existing strength — a deep pool of chip design talent already serving global firms — into a presence further up the physical supply chain.

The instrument

The scheme’s decisive change came on 4 October 2022, when the fab scheme was modified to offer a flat 50 per cent of project cost on a pari-passu basis across all process nodes, replacing node-differentiated support. Where that support is given as equity, the Centre’s share is capped at 49 per cent of total project equity. Implementing guidelines followed on 29 May 2023 and the support runs six years; the rulebook was most recently amended on 8 September 2025.

The flat 50 per cent is the single most important number in Indian chip policy. It means the state carries half the capital risk of a facility whose economics are set by yield — a competence no subsidy can supply.

Where it stands: approvals versus operations

MeitY told the Rajya Sabha on 12 December 2025 that ten units had been approved under the Semicon India Programme, carrying about Rs 1.6 lakh crore of investment and spanning a silicon fab, a silicon carbide fab, advanced packaging and memory packaging. The Union Cabinet approved two further units on 5 May 2026 with cumulative investment above Rs 3,900 crore.

What has actually begun operating is narrower, and the distinction matters more than the headline:

• 31 March 2026 — the Kaynes Semicon plant at Sanand, Gujarat was inaugurated: the first ISM-backed assembly plant to move from construction into operation.
• 4 July 2026 — the CG Semi outsourced semiconductor assembly and test (OSAT) facility at Sanand was inaugurated, the second unit at that site to begin operating within four months.
• 19 April 2026 — groundbreaking in Odisha for what ISM described as India’s first advanced 3D packaging unit, extending the footprint beyond the Gujarat cluster.
• 15 May 2026 — Rajasthan’s first semiconductor plant was announced, widening the spread beyond Gujarat, Assam, Uttar Pradesh and Odisha.

Every unit that has actually started running is on the packaging and assembly side. Commercial fabrication remains under construction. That is not a failure — ATMP/OSAT is the conventional entry point into the industry and it is where India’s cost position is strongest — but it is a materially different claim from “India is making chips,” and the two are routinely conflated.

The design and talent leg

The part of the programme with the least construction risk is the part building on existing strength. Under the Design Linked Incentive scheme, support has gone to 23 companies covering 24 designs across satellite communication, drones, IoT, telecom and AI devices, with free electronic-design-automation tool access for 94 start-ups. The Chips to Start-up programme extended design tools to 397 universities and start-ups; 56 chips designed at more than 46 universities were fabricated at SCL Mohali, and over 67,000 students have been trained.

The wider electronics base it sits on has grown substantially on the ministry’s own figures: manufacturing from Rs 1.9 lakh crore in 2014-15 to Rs 11.32 lakh crore in 2024-25, with exports up from Rs 38,000 crore to Rs 3.26 lakh crore.

The two logics

1. Economic. Capture manufacturing value, build an electronics ecosystem, and cut a large strategic import bill.
2. Strategic autonomy. Chips are a chokepoint in any great-power contest. Domestic capacity, and trusted-partner supply chains, reduce exposure — a calculation sharpened by competition with China and one that ties this programme directly to strategic autonomy.

What comes next: ISM 2.0

NITI Aayog published a Future of India’s Semiconductor Industry roadmap on 29 May 2026, an assessment issued outside MeitY as the first phase neared its successor. Reporting on the successor scheme, India Semiconductor Mission 2.0, indicates the Centre is not keen to cover technology-transfer and land costs under the new programme (The Indian Express) — which would shift more of the risk that Semicon 1.0’s flat 50 per cent absorbed back onto applicants. That reporting is news-tier and the scheme documents are the primary to check when they publish.

What still has to be proven

Fabrication is the hard frontier. A modern fab is enormously capital-, water- and power-intensive, depends on imported tooling and process IP, and lives or dies on manufacturing yield — an operational competence built over years, not bought with incentives. Three questions follow, and this brief tracks them rather than answering them:

• Yield at volume. Whether announced fabrication projects reach volume production at competitive yields, as distinct from being commissioned.
• The materials and tooling layer. Analysts have argued the bet needs a materials strategy, not only a manufacturing one — fabs consume specialty chemicals, gases and substrates India largely imports, and tooling access runs through a small number of foreign suppliers.
• Whether partner-dependence is a bridge or a ceiling. The model is built on partnerships with established foreign chipmakers and equipment firms. Carnegie frames the underlying choice as “build, not buy”; whether the current structure builds capability or rents it is the contested question.

What is contested

The approval figures, investment totals and commissioning dates above are the government’s own, drawn from ISM notifications and a Rajya Sabha reply, and are consistent across those sources. What is disputed is what they demonstrate: whether ten approvals and Rs 1.6 lakh crore of committed investment represent an industry taking root or a pipeline whose hardest stage is still ahead; whether concentrating on packaging first is a sound sequencing or an admission that fabrication is out of reach for now; and whether ISM 2.0’s reported withdrawal of technology-transfer and land support tightens discipline or deters the partners the model depends on. Those are the positions actually held; this brief attributes them and does not adjudicate.

Who owns this topic (and why we’re here)

Search results for India’s chip programme split between two layers that both miss the same thing. Trade and wire coverage tracks each approval and inauguration as a discrete event, and exam-prep explainers restate the scheme architecture at whatever revision they last saw. Neither keeps a running distinction between what has been approved, what is under construction and what is operating — which is the only distinction that tells you where the programme actually is. This brief maintains that ledger against ISM’s own notifications, dates every figure, and is anchored to the semiconductors dossier with the full record.

Maintained topic brief. Analysis by IndiaStand — it characterises the state of play and the range of positions actually held, attributes each claim, and makes no forecast and no recommendation.